Sense Amplifier

Sense Amplifier

A sense amplifier is as important as the memory cell, because
its performance affects the whole chip performance significantly.
The function of the sense amplifier is to read the data

from the storage cell and to magnify the signal level up to
the appropriate logic level to be treated by digital logic gates.
Taking a DRAM sense amplifier as an example, Fig. 7 shows
the schematic diagram of a conventional sense amplifier for
DRAM. This circuit block operates as follows. At the initial
condition, assume that ‘‘H’’ level is stored in MC1. A bit line
pair is precharged and equalized by M1, M2 and M3, and
other MOS transistors are turned off. First, M1, M2, and M3
turn off to set up the preparation stage for sensing. Then, the
selected word line (WL1) is activated by the row address. As
a result, one MOS access transistor and one storage capacitor
is connected to the bit line. This action causes the imbalances
of the bit line pair. The voltage of the bit line changes slightly
because of storage charge in the capacitor of MC1, whereas
the other bit line still remains at the same level. This differ- 
ence can be detected by the sensing node. Sense amplifier 
driver transistors M8 and M9 turn on in order to activate the
amplification function. Then, a small signal value between
the bit line pair becomes a large signal level by the cross-
coupled MOS transistors. The basic function is simple; how-
ever, optimizing the size and timing for each clock is an es-
sential issue for the DRAM system designer.